| Abstract | Hardware description languages (HDLs) are a critical tool in the field of digital system design in both industry and academia. Compared to many software programming languages, HDLs seem to be particularly difficult to learn and master, leading to shortages in HDL designers, particularly as the need for HDL training grows outside of its traditional locus in Computer Engineering to cross-disciplinary projects in fields such as Physics and Biomedical Engineering.
We believe one of the most significant barriers to learning HDLs is the set of complex rules related to concurrency, determinism, and timing. In the popular Verilog language, these rules are governed by a standard known as the Verilog Stratified Event Queue (VSEQ). The VSEQ governs the ordering of statements in the Verilog language, and understanding its rules is essential to understanding the functionality of complex pieces of Verilog code.
Currently, instruction on the VSEQ in the course ECE551 - Digital System Design & Synthesis at UW-Madison is done via 1-2 lectures in class in conjunction with a handout reading. In class, the instructor analyzes a piece of Verilog code and works through its interaction with the VSEQ in a step-by-step fashion. Students are also asked to perform a similar task as part of a graded applied homework assignment.
Anecdotal evidence gathered from recent instructors of the course suggests that VSEQ-related topics generate more student questions via e-mail and office hours than any other topic currently being taught in the course. VSEQ-related mistakes are commonly encountered on homework problems and in the project component of the course.
Therefore, we believe that the instructional materials related to the VSEQ are a good target for revision.
We hypothesize that the existing instructional materials are failing to achieve our learning goals for the following reasons:
· Parallel operation is central to the concept of the VSEQ, where multiple processes are operating concurrently. For a single instructor writing on a blackboard, it is very difficult to visually represent concurrent operation.
· Similarly, it is difficult to represent phenomena such as determinism/non-determinism.
· The existing instructional materials do not thoroughly address diverse learning styles since they mostly use reading/writing and aural material. The visual material is very limited. We believe that visual materials could do a better job of representing concurrency.
· Since much of the material is taught through reading, students who are not native English speakers may have more difficulty learning.
Based on these factors, we hypothesize that the introduction of more visual instructional materials could improve learning outcomes. As part of our study, we will develop interactive instructional tools that demonstrate the concurency rules of the VSEQ using animations and other highly visual approaches. We will evaluate the success of these new approaches compared to the existing materials which focus on reading-based learning. |
